ESP32-C3 simulation: Seeed Studio XIAO
Run merged ESP32-C3 firmware in Sim86. Explore working projects, packet-level Wi-Fi, RF controls, and hardware benchmarks.
The Seeed Studio XIAO ESP32-C3 is a thumb-sized board built around Espressif’s ESP32-C3, a single-core 32-bit RISC-V chip with an integrated 2.4 GHz Wi-Fi radio. It shares the XIAO footprint with the RP2040 board: eleven I/O pins on the silkscreen, USB-C, and a battery connector.
It takes a merged flash image (.bin), not an ELF — the same artifact esptool writes to a real board, containing the bootloader, partition table, and application.
Run firmware on this board
Section titled “Run firmware on this board”Open two controllers sharing a bus or the display and button example. Inspect the merged flash image and circuit before adapting either project. The hardware comparison publishes a separate ESP32-C3 loopback workload with measured traces.
Need a specific peripheral or behavior for your firmware? Contact us to discuss your requirements.
Datasheet
Section titled “Datasheet”The ESP32-C3 datasheet and technical reference manual cover the register map, interrupt matrix, and radio.
| Board pin | ESP32-C3 GPIO | Typical function |
|---|---|---|
| D0 | GPIO2 | GPIO / A0 |
| D1 | GPIO3 | GPIO / A1 |
| D2 | GPIO4 | GPIO / A2 |
| D3 | GPIO5 | GPIO / A3 |
| D4 | GPIO6 | I2C SDA |
| D5 | GPIO7 | I2C SCL |
| D6 | GPIO21 | UART TX |
| D7 | GPIO20 | UART RX |
| D8 | GPIO8 | SPI SCK |
| D9 | GPIO9 | SPI MISO |
| D10 | GPIO10 | SPI MOSI |
| 3V3, 5V, GND | — | Power rails |
Those bus functions are defaults, not fixed wiring. The simulator follows the live ESP32-C3 GPIO matrix for I2C master traffic, including routes across D1–D7, so firmware can choose its SDA and SCL pads at runtime.
The radio is not a pin. Join it to an RF Environment by adding this component’s ID to that room’s members — RF membership is a scene relationship, not a wire.
Firmware that brings up a SoftAP can then be reached from a Wi-Fi Network, including from a real browser tab. Association, DHCP, DNS and TCP all happen over simulated frames, so RF loss and collisions apply.
Internal temperature sensor
Section titled “Internal temperature sensor”The ESP32-C3 temperature sensor measures the silicon die, not room air, and
it has no external pin. Firmware may use ESP-IDF’s
driver/temperature_sensor.h API or access the APB SAR ADC and private analog
range registers directly.
Set ambientTemperatureCelsius in the board configuration to describe the air
around the XIAO; it defaults to 25 °C. The reported die temperature then follows
a deterministic two-stage package/junction model:
- CPU-idle operation warms above ambient.
- Starting Wi-Fi adds radio self-heating; sustained traffic adds a smaller, bounded load based on transmitted and received frames.
- Junction temperature reacts quickly while the tiny board/package heats and cools much more slowly.
- The 8-bit conversion has seeded adjacent-code jitter, a factory-style per-chip eFuse correction, the documented five DAC ranges, clock/reset/power gating, and 300 µs settling.
At the default 25 °C ambient, a fresh board starts near 30 °C, settles in the low 30s while idle, and approaches roughly 60–70 °C under sustained Wi-Fi depending on packet activity. These are useful, repeatable engineering values rather than a promise about the temperature of every physical enclosure or power supply.
const c3 = project.graph.addComponent(Components.XIAO_ESP32C3, { config: { ambientTemperatureCelsius: 30 },});Debug output
Section titled “Debug output”| Channel | Description |
|---|---|
uart0 | Serial console — everything printf/ESP_LOG writes |
The channel streams to the terminal panel live and is readable afterwards with
run.logs({ from: "mcu1:uart0" }).